1. Field of the Invention
The apparatus of the present invention generally relates to data processing systems and more particularly to the interchange of information between a central processing unit and input/output controllers to which peripheral devices are attached.
2. Discussion of the Prior Art
A data processing system usually includes a central processing unit (CPU) which executes software instructions which are stored at addresses, or locations, in main memory. These software instructions are transferred to the CPU sequentially under the control of a program counter. The data that is processed is transferred into and out of the system by way of input/output devices, or peripheral devices, such as teletypewriters, magnetic disks, magnetic tapes or line printers. These peripheral devices are usually interfaced to the CPU and main memory by an interface known as an input/output controller (IOC).
In a system having a plurality of peripheral devices coupled to the CPU via input/output controllers, an orderly system must be provided by which the bidirectional transfer of information may be provided between the IOCs and the CPU and between the IOCs and main memory. This problem becomes more complicated when the CPU and I/O controllers work independently of each other and one device makes an unsolicited request upon the other device for information or for service. For example, the CPU may inquire of an input/output controller the status of an information transfer taking place between a peripheral device attached to the IOC and the main memory. Alternatively, an I/O controller may make a request upon a CPU for the servicing of an interrupt so that software may be informed about the completion of an input/output transfer. In both of these cases, the requesting device may find that the responding device is temporarily busy and unable to immediately respond to the request.
Various methods and apparatus are known in the prior art for interconnecting such a system. One scheme in which the input/output controller is to make a request for service upon the CPU is shown in U.S. Pat. No. 3,866,181 issued to Byron B. Gayman et al and entitled "Interrupt Sequencing Control Apparatus". Another scheme dealing with multiple devices connected to an asynchronous common bus in which the responding unit may respond with a wait response is shown in U.S. Pat. No. 3,993,981 issued to Frank V. Cassarino, Jr. et al and entitled "Apparatus For Processing Data Transfer Requests In A Data Processing System".